Abstract
The yield of VLSI processors with on-chip cache can be enhanced considerably by tolerating cache defects. It has been shown that the performance degradation due to disabling the faulty blocks is small enough for set-associative caches while in the case of direct-mapped caches may be substantial. In this paper we present a reconfigurable cache capable of operating either as direct-mapped (DM) or as two-way set-associative (TW). In this way VLSI processor chips with defective cache blocks are not discarded, attaining a yield enhancement and are also used in the operation mode that minimises the performance degradation. Trace driven simulation has been used to determine the minimum number of faulty blocks after which the TW operation mode is more profitable. This minimum value depends on cache size, block size, the access time of the cache and the miss penalty time. For computing the access time of the caches, an analytical access time model for on-chip caches already proposed in the open literature has been used.
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© 1997 Springer Science+Business Media Dordrecht
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Vergos, H.T., Nikolos, D., Mitsiadis, P., Kavousianos, C. (1997). Reconfigurable CPU Cache Memory Design: Fault Tolerance and Performance Evaluation. In: Reis, R., Claesen, L. (eds) VLSI: Integrated Systems on Silicon. IFIP — The International Federation for Information Processing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35311-1_9
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DOI: https://doi.org/10.1007/978-0-387-35311-1_9
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