Abstract
This paper presents a novel mapping technique, which uses a Boolean matching algorithm based on testing techniques. The matching is detected by checking the controllability and observability of signals in the cell structure against the subject functions of the network. The method was implemented inside the Sis (Touati 1990) synthesis environment. The comparison with the Sis structural mapping shows that the Boolean mapping achieves better results in similar or smaller computing time.
Supported by the EC project KIT #144 LLSynth.
Supported by Capes and UFV-Brazil
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© 1997 Springer Science+Business Media Dordrecht
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Ferreira, R., Trullemans, AM., Jacobi, R. (1997). Boolean Mapping based on Testing Techniques. In: Reis, R., Claesen, L. (eds) VLSI: Integrated Systems on Silicon. IFIP — The International Federation for Information Processing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35311-1_28
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DOI: https://doi.org/10.1007/978-0-387-35311-1_28
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