Abstract
This paper* introduces a new logic transformation that integrates retiming with algebraic and Boolean transformations at the technology-independent level. It offers an additional degree of freedom in sequential network optimization resulting from implicit retiming across logic blocks and fanout stems. The application of this transformation to sequential network synthesis results in the optimization of logic across register boundaries. We have implemented our new technique within the SIS framework and demonstrated its effectiveness in terms of cycle-time minimization on a set of sequential benchmark circuits.
This work has been supported in part by a grant from NSF under contract No. MIP9613864, and in part by the Healey Endowment Grant from the University of Massachusetts. S. Bommu is now with NEC CC Research Labs, Princeton, N.J.
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© 1997 Springer Science+Business Media Dordrecht
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Bommu, S., Ciesielski, M., O’Neill, N., Kalla, P. (1997). Sequential Logic Optimization with Implicit Retiming and Resynthesis. In: Reis, R., Claesen, L. (eds) VLSI: Integrated Systems on Silicon. IFIP — The International Federation for Information Processing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35311-1_27
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DOI: https://doi.org/10.1007/978-0-387-35311-1_27
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