Abstract
A methodology that efficiently translates Estelle formal specifications into a VHDL description, suitable for High Level Synthesis of communication protocols is proposed. The effect of the protocol description style in VILDL, on the result of the LII. S scheduling step is discussed by report to the Dynamic Loop Scheduling algorithm. An example using a test protocol is given.
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© 1997 Springer Science+Business Media Dordrecht
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Pirmez, L., Pedroza, A., Mesquita, A. (1997). High Level Synthesis of Protocols Described by a Formal Description Technique. In: Reis, R., Claesen, L. (eds) VLSI: Integrated Systems on Silicon. IFIP — The International Federation for Information Processing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35311-1_23
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DOI: https://doi.org/10.1007/978-0-387-35311-1_23
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