Abstract
The CORDIC algorithm has been widely used as a powerful and flexible generic architecture to implement many algorithms involving non-trivial arithmetic. However, when using its fastest, i.e. unfolded, implementation it exhibits excessive silicon area demands. Exploiting some peculiarities of the algorithm permits simpler hardware structures in the unfolded case yielding a substantial area reduction. Thus, power consumption is decreased, too. These reductions have no speed penalty. The benefits of the improved architecture have been verified by developing VHDL models and synthesizing sample layouts for comparison purposes.
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© 1997 Springer Science+Business Media Dordrecht
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Timmermann, D., Dolling, S. (1997). Unfolded Redundant CORDIC VLSI Architectures With Reduced Area and Power Consumption. In: Reis, R., Claesen, L. (eds) VLSI: Integrated Systems on Silicon. IFIP — The International Federation for Information Processing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35311-1_21
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DOI: https://doi.org/10.1007/978-0-387-35311-1_21
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