Abstract
Only switches with input buffers offer the possibility to handle effectively the large and full-rate bursts that arise from the transport of data traffic and the burst accumulation within large ATM networks. Efficient contention resolution mechanisms are necessary to prevent output blocking in these input buffered switch architectures and to allow a fair and waste-free utilization of the switch.
This paper first reviews the different types of existing contention resolution mechanisms and shows their limits concerning fairness, scalability, and the possibility to support switching of multicast and prioritized cell streams. Then a new approach is presented that achieves an absolutely fair and efficient contention resolution on the cell level by using modified LAN medium access control (MAC) protocols. The requirements that a MAC protocol has to accomplish are investigated and the excellent performance (using an adapted version of the CRMA-II MAC protocol) of the proposed approach is shown Finally native extensions toward the integration of multicast and prioritized traffic are given and it is demonstrated how this architecture can easily be scaled up to coordinate switches with throughputs of several Terabits per second.
Chapter PDF
Similar content being viewed by others
References
Ahmadi, H. and Denzel, W. (1989): A Survey of Modern High—Performance Switching Techniques, IEEE Journal on Selected Areas in Communications, Vol. 7, No. 7, pp. 1091–1103
ATM Forum (1994): Reliability and Performance Considerations for ABR and VBR+ to support LAN Applications, Traffic Management Subworking Group, 94–0262
Bingham, B. and Bussey, H. (1988): Reservation—Based Contention Resolution Mechanism For Batcher—Banyan Packet Switches, Electronics Letters, 23 June 88, pp. 772 – 773
Conti, M. and Lenzini, L. (1991): A Methodological Approach to an Extensive Analysis of DQDB Performance and Fairness, IEEE J on Sel. Areas in Comm Vol 9 No 1, pp. 76 – 87
Garcia-Haro, J. and Jajszczyk, A. (1994): ATM Shared—Memory Switching Architectures, IEEE Network July/August 1994, pp. 18 – 26
Hluchyj, M. G. and Karol, M. J. (1988): Queueing in High—Performance Packet Switching, IEEE Journal on Selected Areas in Communications Vol. 6 No. 9, pp. 1587 – 1597
Hui, J. Y. and Arthurs, E. (1987): A Broadband Packet Switch for Integrated Transport, IEEE Journal on Selected Areas in Communications Vol. 5 No. 8, pp. 1264 –1273
Karol, M. J. et al. (1987): Input Versus Output Queueing on a Space—Division Packet Switch, IEEE Transactions on Communications Vol. 35
LaMaire R. O. and Serpanos, D. N. (1994): Two—Dimensional Round—Robin Schedulers for Packet Switches with Multiple Input Queues, IEEE/ACM Trans. on Netw., pp. 471 – 482
Lemppenau, W. W. et al. (1993): ATM Implementation of the CRMA—H Dual Ring LAN and MAN, Proceedings of EFOC&N 93, The Hague, June 30 – July 2, 1993
Main, J. and Sarkies, K. (1995): Cell Scheduling Using Status Arrays in Input Buffered ATM Switches, Proceedings of the First IEEE Worksh. on Broadb. Switching Syst., Poznan, Polen
Matsunaga, H. and Uematsu, H. (1991): A 1.5 Gb/s 8x8 Cross—Connect Switch Using a Time Reservation Algorithm, IEEE Journal on Selected Areas in Communications, pp. 1308 –1317
Obara, H. (1991): “Optimum Architecture for Input Queueing ATM Switches”, Electronics Letters, 28th March 1991, pp. 555 – 557
Obara, H. and Hamazumi, Y. (1992): Parallel Contention Resolution Control for Input Queueing ATM Switches, Electronics Letters, 23rd April 1992, pp. 838 – 839
Simcoe, R. J. and Pei, T.-B. (1995): Perspectives on ATM Switch Architecture and the Influence of Traffic Pattern Assumptions on Switch Design, Computer Comm. Review, pp. 93 – 105
van As, H. et al. (1991): CRMA—II: A Gbit/s MAC Protocol for Ring and Bus Networks with Immediate Access Capability, Proceedings of EFOC/LAN 91, London, June 19–21, 1991
van As, H. and Lemppenau, W. W. (1992): Performance of CRMA—II: A Reservation—Based Fair Media Access Protocol for Gbit/s LANs and MANs, Proceedings of EFOC/LAN 92, Paris, June 22–24, 1992
Worster, T. et al. (1995): Buffering and Flow Control for Statistical Multiplexing in an ATM Switch, Proceeding of the ISS 95, Berlin, Germany, April 1995, Paper no. 488
Xerox Corp. (1993): A Switching Network, European Patent Application, Publication Number: 0 571 166 A2, 24 Nov 1993.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1996 IFIP International Federation for Information Processing
About this chapter
Cite this chapter
Kirstäer, A. (1996). Fair and Flexible Contention Resolution for Input Buffered ATM Switches Based on LAN Medium Access Control Protocols. In: Mason, L., Casaca, A. (eds) Broadband Communications. BC 1996. IFIP Advances in Information and Communication Technology. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-34987-9_31
Download citation
DOI: https://doi.org/10.1007/978-0-387-34987-9_31
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-5041-2960-2
Online ISBN: 978-0-387-34987-9
eBook Packages: Springer Book Archive