Abstract
To be efficient, a design methodology has to take into account the following user requirements: fast prototyping in order to satisfy the time to market constrain., the production of efficient architecture, the comparison of the complexity of different DSP algorithmic solutions. These requirements may be associated to user constraints such as real time processing, cost or power consumption, the re-use of previous developments.
Such a design methodology has been developed and integrated into the tool GAUT. From the VHDL behavioural specification of a DSP algorithm, a time constraints and a technologic library (FPGA, standard cells), the dedicated pipeline architecture is synthesized. This VHDL description is then computed by a logic synthesis tool. This design flow, which produce quickly efficient dedicated architectures, is validated on some digital signal processing applications like acoustic echo cancellation and ADPCM.
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References
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Diguet J.P., Sentieys O., Philippe J.L., Martin E.; “How Specify an Algorithm in VLSI architectural Synthesis, a Vocal Coding Application”; VLSI Signal Processing VII; La Jolla-San Diego; October 94; pp 346–355.
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© 1995 IFIP International Federation for Information Processing
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Philippe, J.L., Sentieys, O., Diguet, J.P., Martin, E. (1995). Synthesis: From Digital Signal Processing Specifications to Layout. In: Saucier, G., Mignotte, A. (eds) Logic and Architecture Synthesis. IFIP Advances in Information and Communication Technology. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-34920-6_31
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DOI: https://doi.org/10.1007/978-0-387-34920-6_31
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-5041-2923-7
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