Abstract
This paper describes the large scale application of logic synthesis and formal verification to the design of the CPU and caches of the high-end series of the Bull DPS7000 mainframe family. The logic CAD suite used for supporting the design of this system proved its efficiency on very complex integrated circuits. The key feature of this logic design environment is the methodology that integrates a set of logic synthesis and formal verification techniques to build an effective logic-design system to support the design of high-performance circuits.
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© 1995 IFIP International Federation for Information Processing
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Nguyen, H.N., Ducousso, L. (1995). BONSAI: A pragmatic approach to Logic Synthesis and Formal Verification. In: Saucier, G., Mignotte, A. (eds) Logic and Architecture Synthesis. IFIP Advances in Information and Communication Technology. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-34920-6_3
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DOI: https://doi.org/10.1007/978-0-387-34920-6_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-5041-2923-7
Online ISBN: 978-0-387-34920-6
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