Abstract
This paper describes a novel technique for module-selection exploration. The approach selects from a library containing a wide range of implementations to provide Delay/Area Trade-Off information for the architecture in question. The Jiggle Algorithm, which is a modified natural algorithm, is based on Darwinian and accelerated evolution ideas and provides effective computation time — results trade-off. Instead of starting the Jiggle Algorithm with a single seed, a re-generative multiple-seed approach is taken which drastically reduces the chance of getting trapped in a local minimum. A more appropriate ‘cost function’ is used in the natural algorithm and a suitable metric is used to evaluate the quality of the DATO graphs produced.
Chapter PDF
Similar content being viewed by others
References
Bidet E., C.Joanblanq and P.Senn, (1993) GENRIF: An integrated VLSI FIR Filter Compiler, European Design Automation Conference, 466–471.
Bruton, L.T., (1975) Low-Sensitivity Digital Ladder Filters, IEEE Transactions on Circuits and Systems, Vol. CAS-22, No. 3.
Cain G.D., A.Yardim, (1990) Darwinian Design of Digital Filters, Proc IEEE Workshop on Genetic Algorithms, Simulated Annealing and Neural Nets Applied to Problems in Signal/Image Processing and Communications, 1–14.
Kale I., P.Belloni, G.D.Cain, E.Del Re, (1993) Guided Simulated Annealing with Tempering for FIR Filter Design Via Z-Plane Zero Manipulation, Proc. Int. Conf on Digital Signal Processing, 390–395.
Karkowski I., (1993) Circuit Delay Optimization as a Multiple Choice Linear Knapsac Program, European Design Automation Conference, 419–423.
Landman P.E., J.M.Rabaey, (1993) Power Estimation for High Level Synthesis, European Design Automation Conference, 361–366.
Rechtin E., (1992) The Art of Systems Architecting, IEEE Spectrum, 66–69, October.
Sakouti, K., P.Abouzeid, M.Belrhiti, M.Crastes, and G.Saucier, (1993) Coherent Optimization Strategies for Multilevel Synthesis, European Design Automation Conference, 378–385.
Timmer A.H., M.J.M.Heijligers, L.Stok, and J.A.G.Jess, (1993) Module Selection and Scheduling using Unrestricted Libraries, European Design Automation Conference, 547–551.
Turner, L.E and B.K. Ramesh, (1986) Low Sensitivity Digital LDI Ladder Filters with Elliptic Magnitude Response, IEEE Transactions on Circuits and Systems, Vol. CAS-33, No. 7.
Wehn N., M.Held, and M.Glesner, (1991) A Novel Scheduling/Allocation Approach for Datapath Synthesis based on Genetic Paradigms, Proc. Int. IFIP Workshop on Logic and Architecture Synthesis, 47–56.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1995 IFIP International Federation for Information Processing
About this chapter
Cite this chapter
Rouse, C.J., Carter, A.J. (1995). Delay/Area Trade-Off Exploration Using an Architectural Jiggling Algorithm. In: Saucier, G., Mignotte, A. (eds) Logic and Architecture Synthesis. IFIP Advances in Information and Communication Technology. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-34920-6_26
Download citation
DOI: https://doi.org/10.1007/978-0-387-34920-6_26
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-5041-2923-7
Online ISBN: 978-0-387-34920-6
eBook Packages: Springer Book Archive