Abstract
High level synthesis has long relied on point models for RT level components, where the area and delay of a component are assumed to be constant for a given style. Nowadays, many synthesis algorithms attempt to incorporate physical design information into the design process so as to better guide the synthesis tasks. In this work, we explore the combined effect of style and aspect ratio variations on the area and delay of RT level components, and on RT level designs which use such components. Our results indicate that point models are inadequate for use in the synthesis process due to the large variations in the area and delay that occur when component styles and aspect ratios are varied. We believe that our results have some deep implications with respect to the flow of the design tasks during high level synthesis.
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© 1995 IFIP International Federation for Information Processing
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Jha, P., Ramachandran, C., Kurdahi, F., Dutt, N. (1995). Towards Better Accounting of Physical Design Effects in High-Level Synthesis. In: Saucier, G., Mignotte, A. (eds) Logic and Architecture Synthesis. IFIP Advances in Information and Communication Technology. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-34920-6_25
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DOI: https://doi.org/10.1007/978-0-387-34920-6_25
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-5041-2923-7
Online ISBN: 978-0-387-34920-6
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