Abstract
A general decomposition concept is presented in this paper. The main strategy behind the presented Multilevel Decomposition Method is striking a balance between serial decomposition and parallel decomposition. The method is applicable to a variety of Field Programmable Gate Arrays and allows trading-off area and delay of final implementation. The results prove that the method is efficient and does not suffer from its generality.
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© 1995 IFIP International Federation for Information Processing
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Łuba, T., Selvaraj, H., Nowicka, M., Kraśniewski, A. (1995). Balanced multilevel decomposition and its applications in FPGA-based synthesis. In: Saucier, G., Mignotte, A. (eds) Logic and Architecture Synthesis. IFIP Advances in Information and Communication Technology. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-34920-6_10
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DOI: https://doi.org/10.1007/978-0-387-34920-6_10
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-5041-2923-7
Online ISBN: 978-0-387-34920-6
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