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Abstract

A specification written in the ISO standardized Estelle language can be translated into the standard hardware description language VHDL. In this paper we present such a translator and we discuss an example of its application. The Estelle formal description technique is used for specification and validation of communication protocols. VHDL is considered as an intermediate step, using of the existing simulation and synthesis tools.

Keywords

Estelle VHDL protocol prototyping 

References

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Copyright information

© IFIP International Federation for Information Processing 1996

Authors and Affiliations

  • Jacek Wytrębowicz
    • 1
  1. 1.Institut National des TélécommunicationstFourierFrance

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