A methodology for the implementation of protocols in hardware from a formal description

  • L. Pirmez
  • A. Pedroza
  • A. Mesquita
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT)


A methodology1 that efficiently translates Estelle formal specifications into a Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) description, suitable for the high level syntesis of an integrated circuit, is proposed. It will be shown that, in order to efficiently map Estelle into VHDL, a number of constrains must be imposed on the set of possible constructs within each language. An example based on the specification of a high speed protocol is discussed.


Protocol high-level synthesis VLSI VHDL Estelle. 


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  19. A. Mesquita received the E.E. degree from PUC/MG, the M.Sc. degree from PUC/RJ and the Docteur d’Etat degree from Université Paul Sabatier of Toulouse, France. Current research interests: Circuits and Systems Theory, VLSI circuit design and Signal processing. Associate Professor at COPPE/UFRJ.Google Scholar
  20. A. Pedroza received the E.E. degree from UFRJ, the M.Sc. degree from COPPE/UFRJ and the Doctorat degree from Université Paul Sabatier/LAAS. Current research interests: Formal Specification, Verification and Implementation of Protocol. Associate Professor at UFRJ.Google Scholar
  21. L. Pirmez received the E.E. degree from UFRJ, the M.Sc. degree from COPPE/UFRJ and prepares a D. Sc. thesis at COPPE/UFRJ. Current research interests: Formal Specification, Verification and Implementation of Protocol.Google Scholar

Copyright information

© IFIP International Federation for Information Processing 1996

Authors and Affiliations

  • L. Pirmez
    • 1
    • 2
  • A. Pedroza
    • 1
    • 3
  • A. Mesquita
    • 1
  1. 1.Coppe/UFRJ - Program of Electric EngineeringRio de Janeiro RJBrazil
  2. 2.NCE/UFRJ - Electronic Computer CentreRio de Janeiro RJBrazil
  3. 3.EE/UFRJ - Department of ElectronicsRio de Janeiro RJBrazil

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