Abstract
Recently, some studies for developing hardware circuits using LOTOS as a hardware description language have been proposed. In this paper, we introduce a LOTOS-like language called LOTOS/HD. Although LOTOS/HD can treat I/O parameters, LOTOS/HD expressions are functionally closed to Basic LOTOS expressions whose LTS’s are finite. Then, we propose a technique for synthesizing hardware circuits semi-automatically from LOTOS/HD expressions. As the target circuits, synchronous sequential circuits are considered. In the proposed technique, first, the designers describe a specification S of a synchronous sequential circuit in LOTOS/HD where they only describe which values should be calculated and how such values are calculated using some functions implemented as combinational logic circuits. Next, from the data dependency relations and the temporal ordering of the events in S, a candidate C of sequential circuits implementing S is derived where C is also written in LOTOS/HD. The derived circuit C is a correct implementation of S if C satisfies some conditions. If C does not satisfy the conditions, the designers must modify C so that the conditions hold. The variables and functions in C are allocated to the registers and combinational logic circuits, respectively. Using a data path allocation technique, the connections between their components are decided automatically.
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© 1995 Springer Science+Business Media Dordrecht
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Higashino, T., Yasumoto, K., Kitamichi, J., Taniguchi, K. (1995). Hardware Synthesis from a Restricted Class of LOTOS Expressions. In: Vuong, S.T., Chanson, S.T. (eds) Protocol Specification, Testing and Verification XIV. IFIP Advances in Information and Communication Technology. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-34867-4_28
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DOI: https://doi.org/10.1007/978-0-387-34867-4_28
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