Abstract
With the advance of semiconductor scaling, smaller devices become more vulnerable to an SEU (single event upset, i.e. neutron hit etc.) and operating margin of the circuits is reduced both due to reduced operating voltage and larger process variations. Robust circuit design alone cannot solve these problems. Micro-architectural techniques for avoiding defects and error detection and correction microarchitecure can significantly reduce the probability of failure and enhance the yield and the reliable operation of a microprocessor. The failure mechanisms of nanometer class semiconductor VLSI circuits are described as a background. Then concept and methods of error detection and correction are described, followed by microarchitecture/logic design error detection and recovery techniques. Commercial microprocessors using error detection and recovery techniques are also presented.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Li, X.-Y. et al., “An effective method of characterization poly gate CD variation and Its impact on product performance and yield”, Proc. Int. Symp. Semicond. Manuf., 2003, 259–262.
Nagase, M.; Tokashiki, K. “Advanced gate etching for accurate CD control for 130-nm node ASIC manufacturing”, 2004 17(3), 281–285.
Schellenberg, F. “A little light magic [optical lithography]”, Spectrum IEEE, 2003, 40(9), 34–39.
Asenov, A.; Kaya, S.; Brown, A.R. “Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness”, Electron Devices, 2003 50(5), 1254–1260.
Asenov, A. “Random dopant induced threshold voltage lowering and fluctuations in sub 0.1 micron MOSFETs: A 3D ‘atomistic’ simulation study,” IEEE Trans. Electron Dev., 1998, 45, 2505–2513.
Pollack, F. “New microarchitecture challenges in the coming generations of CMOS”, 1999. MICRO-32. Keynote, 32nd Annual International Symposium on Microarchitecture.
Gelsinger, P.P. “Microprocessors for the new millennium: challenges, opportunities, and new frontiers,” IEEE Int. Solid-State Circuits Conf., 2001, XLIV, 22–25.
Chen, H.H.; Ling, D.D. “Power supply noise analysis methodology for deep-submicron Vlsi chip design”, Proc. 34th Design Automation Conf., 1997, 638–643.
Zhao, S.; Roy, K.; Koh, C.-K. “Estimation of inductive and resistive switching noise on power supply network in deep sub-micron CMOS circuits”, Proceedings, Int. Conf. Computer Design, 2000, 65–72.
Prakash, M. “Cooling challenges for silicon integrated circuits”, Proc. 9th Int. Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems, 2004. (ITHERM’ 04) 2, 705–706
Bota, S.A. et al., “Within die thermal gradient impact on clock-skew: a new type of delay-fault mechanism”, Proc., Int. Test Conf., 2004, 1276–1283
Banerjee, K.; Mehrotra, A. “Global (interconnect) warming”, Circuits and Devices IEEE, 17(5), 16–32
Ziegler J.F. et.al., “IBM experiments in soft fails in computer electronics (1978–1994)”, IBM J. Res. Dev. 1996, 40(1), 3–18
Ziegler, J.F. “Terrestrial cosmic rays”, IBM J. Res. Dev., 1996, 40(1), 19–40.
Freeman, L.B. “Critical charge calculations for a bipolar SRAM array”, IBM J. Res. Dev. 1996, 40(1), 119–130.
Baumann, R. “The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction,” IEDM Tech. Dig., December 2002, 329–332.
Tosaka, Y.; Ehara, H.; Igeta, M. et al., “Comprehensive study of soft errors in advanced CMOS circuits with 90/130 nm technology,” IEDM Tech. Dig., December 2004, 941–944.
Liden, P. et al., “On latching probability of particle induced transient in combinational networks”, Int. Symp. on Fault Tolerant Computing FTCS24, June 1994, 340–349.
http://public.itrs.net/Files/2003ITRS/Home2003.htm
Smith, R. et al., “32K and 16K MOS RAMs using laser redundancy techniques”, Solid-State Circuits Conference. Digest of Technical Papers, 1982, XXV, 252–253.
Horowitz, M.; Dally, W. “How scaling will change processor architecture”, ISSCC Dig Tech Pap. 2004, 132–133.
Ando, H.; Tzartzanis N.; Walker, W. “A case study: power and performance improvement of a chip multi-processor for transaction processing”, IEEE Trans. VLSI Syst., July 2005 (To be published).
Alves, L.C. et al., “RAS design for the IBM eServer z900”, IBM J. Res. Dev., 2002, 46(4/5), 503–522.
Pham, D. et al., “The design and implementation of a first-generation CELL Processor”, Tech. Digest, Int. Solid-State Ciruit Conf., February 2005, 184–185.
Wuu, J. et al., “The asynchronous 24MB on-chip level-3 cache for a dual-core Itanium-family processor”, Tech. Digest, Int. Solid-State Ciruit Conf., February 2005, 488–489.
Nelson, V.P. “Fault-tolerant computing: fundamental concepts”, IEEE Computer, 1990, 23(7), 19–25.
Berger, J. “A note on error detecting codes for asymmetric channel”, Info Control, 1961, 68–73
Fujiwara, E.; Pradhan, D.K. “Error-control coding in computers”, IEEE Computer, 1990, 23(7), 63–72.
Hsiao, M.Y. “A class of optimal minimum odd-weight-column SECDED codes”, IBM J. Res. Dev., 1970, 14, 395–401.
Kaneda, S.; Fujiwara, E. “Single byte error correcting-double byte error Detecting codes for memory systems”, IEEE Trans. Computers, July 1982, C31(7), 737–739.
Reed I.S.; Solomon, G. “Polynomial codes over certain finite fields”, J. Soc. Indust. Appl. Math” 1960, 8, 300–304.
Gorshe, S.; Bose, B. “A self-checking ALU design with efficient codes”, 14th VLSI Test Symp. April 1996, 157–161.
Nocolaidis, M. “Efficient implementations of self-checking adders and ALUs”, Int. Symp. on Fault Tolerant Computing FTCS23, June 1993, 586–595
Sparmann, U.; Reddy, S. “On the effectiveness of residue checking for parallel two’s complement multipliers”, IEEE Trans VLSI Systems, 1996, 4(2), 219–228.
Matrosova, A.; Ostanin, S. “Self-checking FSM design with observing only FSM outputs”, Proc. 6th Int. On-Line Testing Workshop, 2000. 153–154.
Goloubeva, O. et al., “Soft-error detection using control flow assertions”, Int. Symp. on Defect and Fault Tolerance in VLSI Systems, November 2003, 581–588.
Hint, D.B.; Marinos, P.N. “A general purpose cache-aided rollback error recovery (CARER) technique”, 17th Symp. on Fault Tolerant Computing, 1987, 170–175
Ahmed, R.E.; Frazier R.C.; Marinos, P.N. “Cache-aided rollback recovery (CARER) algorithms for shared-memory multiprocessor systems”, Digest of Papers, 20th Int. Symp. on Fault-tolerant Computing, 1990, 82–88.
Bowen, N.S.; Pradhan, D.K. “Processor-and memory-based checkpoint and rollback recovery”, IEEE Computer, 1993, 26(2), 22–31.
Ando, H.; Kitamura, T.; Shebanow, M.; Butler, M. US Patent 6,519,730 “Computer and error recovery method for the same”; February 11, 2003, Filed on March 16, 2000
Sato, T. “Exploiting instruction redundancy for transient fault tolerance”, Int. Symp. on Defect and Fault Tolerance in VLSI Systems, November 2003, 547–554.
Webb, C.F.; Liptay, J.S. “A high-frequency custom CMOS S/390 microprocessor”, IBM J. Res. Dev. 1997, 41(4/5), 463–474.
Schwarz, E.M. et al., “The microarchitecture of the IBM eServer z900 processor”, IBM J. Res. Dev. 2002, 46(4/5), 381–396.
Rusu, S. et al., “A 1.5-GHz 130-nm Itanium 2 processor with 6-MB on-die L3 cache”, IEEE J. Solid-State Circuits, 2003, 38(11), 1887–1895.
Naffziger, S.; Stackhouse, B.; Grutkowski, T. “The implementation of a 2-core multithreaded Itanium®-family processor”, ISSCC Dig. Tech. Pap., 2005, 182–183.
Inoue, A. “Fujitsu’s new SPARC64 V for mission-critical servers”, Microprocessor Forum 2002.
Ando, H. et al., “A1.3GHz fifth-generation SPARC64 microprocessor”, IEEE J. Solid-State Circuits, 2003, 11, 1896–1903.
Slegel, T.J.; Pfeffer E.; Magee, A. “The IBM eServer z990 microprocessor”, IBM J. Res. Dev. 2004, 48(3/4), 295–310.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer
About this chapter
Cite this chapter
Ando, H. (2006). Microprocessor Architecture for Yield Enhancement and Reliable Operation. In: Oklobdzija, V.G., Krishnamurthy, R.K. (eds) High-Performance Energy-Efficient Microprocessor Design. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-34047-0_9
Download citation
DOI: https://doi.org/10.1007/978-0-387-34047-0_9
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-28594-8
Online ISBN: 978-0-387-34047-0
eBook Packages: EngineeringEngineering (R0)