Abstract
Since 1990 many floating-point units have been designed using a fused multiply-add dataflow. This type of design has a huge performance advantage over a separate multiplier and adder. With one compound operation, effectively two dependent operations per cycle can be achieved. Even though a fused multiply-add dataflow is now common in today’s microprocessors, there are many details which have never been discussed in papers. This chapter shows the implementation of the different parts of the fused multiply-add dataflow including the counter tree, suppression of sign extension encoding, leading zero anticipation, and end around carry adder design. This chapter illustrates algorithms and implementation details used in today’s floating-point units that have been passed down from designer to designer, becoming the folklore of floating-point unit design.
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Schwarz, E.M. (2006). Binary Floating-Point Unit Design. In: Oklobdzija, V.G., Krishnamurthy, R.K. (eds) High-Performance Energy-Efficient Microprocessor Design. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-34047-0_8
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DOI: https://doi.org/10.1007/978-0-387-34047-0_8
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