Processor Core and Low-Power SOC Design for Embedded Systems

Abstract

A processor core SH-X based on SuperH™ architecture is described. It is implemented in a 130-nm CMOS process running at 400 MHz achieving 720 MIPS and 2.8 GFLOPS at a power of 250 mW under worst-case conditions. It has a dual-issue seven-stage pipeline architecture, but reaches 1.8 MIPS/MHz, which is equivalent to the previous five-stage processor. The processor meets the requirements of a wide range of applications, and is suitable for digital appliances aimed at the consumer market, such as cellular phones, digital still/video cameras, and car navigation systems. In this chapter a system-on-a-chip (SOC) implementation called SH-Mobile3 that uses SH-X core and low-power circuit technology’s also described. The SOC applies power-switch circuit and low-leakage SRAM and achieves less than 100µA in a stand-by mode.