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Probing Semiconductor Technology and Devices with Scanning Spreading Resistance Microscopy

  • Chapter
Scanning Probe Microscopy

Abstract

As the downscaling in semiconductor industry continues, the correct operation of devices becomes critically dependent on the precise location and activation of the dopants in two dimensions. For Si technology, Duane had already determined in 1996 that, in the 0.25-μm CMOS technology, a 10-nm decrease in the channel length was responsible for a more than 10% increase in the gate-to-drain overlap capacitance [1]. In the 65-nm devices processed today, effects of shifts in lateral position of a few nanometers or of variations in concentration of a few percent in the channel are drastically more pronounced.

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Author information

Authors and Affiliations

  1. Kapeldreef 75, B-3001, Leuven, Belgium

    Dr. P. Eyben, Prof. W. Vandervorst & Dr. M. Xu

  2. Infineon Technologies, 05452, Essex Junction, VT, USA

    D. Alvarez

  3. Z. I. de la Gaudrée, Veeco instruments S.A.S., 11 rue Marie Poussepin, BP 43, 91412, Dourdan, France

    Dr. M. Fouchier

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  1. Dr. P. Eyben
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  2. Prof. W. Vandervorst
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  3. D. Alvarez
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  4. Dr. M. Xu
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  5. Dr. M. Fouchier
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Editor information

Editors and Affiliations

  1. Oak Ridge National Laboratory, Oak Ridge, TN, 37831, USA

    Sergei Kalinin

  2. Dept. Materials Science and Engineering, North Carolina State University, Raleigh, NC, 27695, USA

    Alexei Gruverman

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Eyben, P., Vandervorst, W., Alvarez, D., Xu, M., Fouchier, M. (2007). Probing Semiconductor Technology and Devices with Scanning Spreading Resistance Microscopy. In: Kalinin, S., Gruverman, A. (eds) Scanning Probe Microscopy. Springer, New York, NY. https://doi.org/10.1007/978-0-387-28668-6_3

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