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Compilers for Reconfigurable Architectures

  • João M. P. CardosoEmail author
  • Pedro C. Diniz
Chapter
  • 449 Downloads

Abstract

This chapter describes the most prominent academic efforts on compilation and synthesis of application codes written in high-level programming languages to reconfigurable architectures. The maturity of some of the compilation and mapping techniques described in Chaps. 4 and 5, and the stability of the underlying reconfigurable technologies, have enabled the emergence of commercial compilation solutions, such as the MAP compiler from SRC Computers [292] and the High-Level Compiler from Nallatech [223], both of which support the mapping of programs written in a subset of the C programming language to FPGAs.

Keywords

Intermediate Representation Communicate Sequential Process Synthesis Tool Spatial Partitioning Temporal Partitioning 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  1. 1.Technical University of Lisbon/IST INESC-IDLisboaPortugal

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