Compilers for Reconfigurable Architectures
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This chapter describes the most prominent academic efforts on compilation and synthesis of application codes written in high-level programming languages to reconfigurable architectures. The maturity of some of the compilation and mapping techniques described in Chaps. 4 and 5, and the stability of the underlying reconfigurable technologies, have enabled the emergence of commercial compilation solutions, such as the MAP compiler from SRC Computers  and the High-Level Compiler from Nallatech , both of which support the mapping of programs written in a subset of the C programming language to FPGAs.
KeywordsIntermediate Representation Communicate Sequential Process Synthesis Tool Spatial Partitioning Temporal Partitioning
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