Mapping and Execution Optimizations

  • João M. P. CardosoEmail author
  • Pedro C. Diniz


This chapter describes important aspects related to the mapping of computations to reconfigurable architectures. The inherently spatial nature of these architectures, their heterogeneity and the invariable limitations of its physical resources, makes this mapping an extremely challenging task. Compilers and tools must judiciously balance the use of different kinds of resources in space and time, engaging in algorithmic and mapping techniques similar to the ones used in the context of lowlevel hardware synthesis, albeit with mapping choices that can be leveraged at much higher levels of abstraction.


Memory Access Clock Cycle Hardware Implementation Hardware Resource Task Graph 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  1. 1.Technical University of Lisbon/IST INESC-IDLisboaPortugal

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