Compilation and Synthesis Flows

  • João M. P. CardosoEmail author
  • Pedro C. Diniz


When mapping applications to reconfigurable computing platforms composed of general-purpose processors (GPP) and reconfigurable architectures, compilers must assume the dual role of compiling for a known instruction-set architecture (ISA) and synthesizing an application-specific architecture to be implemented with the hardware resources of the underlying reconfigurable architecture. The compiler is thus responsible for the definition of the specific organization of the computing engine implemented in the reconfigurable processing units (RPUs). As reconfigurable systems offer the possibility of multiple processing elements (PEs), compilers must deal with the many aspects of parallel computing and all its associated compilation techniques, namely, processor synchronization, data partitioning, and code generation. It is thus not surprising that compilation for reconfigurable systems is notoriously hard as compilers must weave, in a coherent and effective way, techniques from parallel computing with techniques from traditional hardware synthesis.


Clock Cycle Hardware Resource Intermediate Representation Array Variable Communicate Sequential Process 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  1. 1.Technical University of Lisbon/IST INESC-IDLisboaPortugal

Personalised recommendations