Dynamic Circuit Design Considerations

SOI’s favorable power and performance characteristics makes this technology appealing to a wide range of market applications. Its reduced capacitance and increased transconductance makes it attrative specifically to high performance applicationns. It follows, then, that it would be counterproductive to eliminate aggressive high speed circuit styles which may be at risk due to some of SOI’s idiosyncrasies described in the last chapter. In this chapter, practices are discussed which help the dynamic logic circuit designer both reduce the temporal contribution to variation and avoid hazardous parasitic responses, without the need to eliminate high speed topologies from the design.