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Part of the book series: Lecture Notes in Control and Information Sciences ((LNCIS,volume 226))

Abstract

Coset enumeration is a most important procedure for investigating finitely presented groups. We present a practical parallel procedure for coset enumeration on shared memory processors. The shared memory architecture is particularly interesting because such parallel computation is both faster and cheaper. The lower cost comes when the program requires large amounts of memory, and additional CPU’s allow us to lower the time that the expensive memory is being used.

Rather than report on a suite of test cases, we take a single, typical case, and analyze the performance factors in-depth. The parallelization is achieved through a master-slave architecture. This results in an interesting phenomenon, whereby the CPU time is divided into a sequential and a parallel portion, and the parallel part demonstrates a speedup that is linear in the number of processors. We describe an early version for which only 40% of the program was parallelized, and we describe how this was modified to achieve 90% parallelization while using 15 slave processors and a master. In the latter case, a sequential time of 158 seconds was reduced to 29 seconds using 15 slaves.

Supported in part by NSF Grant CCR-9509783.

Supported in part by the Australian Research Council.

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© 1997 Springer-Verlag London

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Cooperman, G., Havas, G. (1997). Practical parallel coset enumeration. In: Cooperman, G., Michler, G., Vinck, H. (eds) Workshop on High Performance Computing and Gigabit Local Area Networks. Lecture Notes in Control and Information Sciences, vol 226. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3540761691_3

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  • DOI: https://doi.org/10.1007/3540761691_3

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-76169-3

  • Online ISBN: 978-3-540-40937-3

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