Multi-level simulator for VLSI on the parallel object-oriented machine

  • E. Aposporidis
  • F. Lohnert
Project 415 Presentations
Part of the Lecture Notes in Computer Science book series (LNCS, volume 365)


Simulation is a key element in modern and future digital circuit design. However, simulation becomes a bottleneck with increasing design complexity. There are mainly two ways to get out of this situation: reduction of the simulation load through multi-level simulation and acceleration of the simulation through exploitation of parallelism.

This paper reports of a new Parallel Multi-Level VLSI Simulator (PMLS) for general purpose parallel machines which combines multi-leveling and exploitation of parallelism at the circuit level.

The VLSI simulator is implemented in the object-oriented language POOL and runs on the DOOM machine.

The paper surveys briefly the principles of digital circuit simulation, as well as the possibilities of exploiting parallelism, and describes the design and implementation of the simulator. Preliminary performance figures are also given.


Time Stamp Abstraction Level Digital Circuit Event List Gate Level 
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Copyright information

© Springer-Verlag Berlin Heidelberg 1989

Authors and Affiliations

  • E. Aposporidis
    • 1
  • F. Lohnert
    • 1
  1. 1.AEG AktiengesellschaftBerlin Research InstituteBerlin 51

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