Abstract
Designs of delay insensitive circuits must be proven correct in two different respects. First it must be demonstrated that a design meets its functional specification. Second it must be assured that it tolerates arbitrary delays in its individual components. The latter proof requires a model explicitly mentioning wire delays, whereas the former is much easier carried out in a model neglecting such delays.
In this paper we show how explicit treatment of wire delays can be substituted by a set of implementation conditions imposed on a model neglecting wire delays. When the conditions are satisfied, the circuit is assured to be delay insensitive.
The implementation conditions are directed towards circuits consisting of self-timed elements using delay insensitive coding for data transfer.
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© 1989 Springer-Verlag Berlin Heidelberg
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Gammelgaard, A. (1989). Implementation conditions for delay insensitive circuits. In: Odijk, E., Rem, M., Syre, JC. (eds) PARLE '89 Parallel Architectures and Languages Europe. PARLE 1989. Lecture Notes in Computer Science, vol 365. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3540512845_49
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DOI: https://doi.org/10.1007/3540512845_49
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