Implementation conditions for delay insensitive circuits

  • Anders Gammelgaard
Submitted Presentations
Part of the Lecture Notes in Computer Science book series (LNCS, volume 365)


Designs of delay insensitive circuits must be proven correct in two different respects. First it must be demonstrated that a design meets its functional specification. Second it must be assured that it tolerates arbitrary delays in its individual components. The latter proof requires a model explicitly mentioning wire delays, whereas the former is much easier carried out in a model neglecting such delays.

In this paper we show how explicit treatment of wire delays can be substituted by a set of implementation conditions imposed on a model neglecting wire delays. When the conditions are satisfied, the circuit is assured to be delay insensitive.

The implementation conditions are directed towards circuits consisting of self-timed elements using delay insensitive coding for data transfer.


Transition System Single Activation Opposed Activation Reachable State Delay Model 
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Copyright information

© Springer-Verlag Berlin Heidelberg 1989

Authors and Affiliations

  • Anders Gammelgaard
    • 1
  1. 1.Computer Science DepartmentÅrhus University Ny MunkegadeÅrhus C

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