Architecture of a communication network processor

  • W. G. P. Mooij
  • A. Ligtenberg
Submitted Presentations
Part of the Lecture Notes in Computer Science book series (LNCS, volume 365)


This article describes the architecture and the design of a high speed packet-switched communication network for multi-processor systems. It consists of a autonomous communication layer connected to a computational layer. The proposed network architecture uses a store and forward communication mechanism to maximally share resources. Each node in the network dynamically forwards messages between a source and a destination using the adaptive bounding box algorithm. In combination with a small message size and parallel datapaths the routing speed is maximized. The network uses minimum sized message queues and dynamically avoids blocked communication links in order to reduce the communication delay. Manufacturing constraints of present planar VLSI technology favours a regular locally connected network topology, e.g. a mesh. A custom VLSI prototype of the communication processor for the network architecture demonstrates the feasibility of the basic architecture.


Destination Address Output Direction VLSI Implementation Communication Node Virtual Path 
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Copyright information

© Springer-Verlag Berlin Heidelberg 1989

Authors and Affiliations

  • W. G. P. Mooij
    • 1
  • A. Ligtenberg
    • 1
  1. 1.Faculty of Mathematics and Computer ScienceUniversity of AmsterdamAmsterdam

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