The Synchronous Dataflow MAchine: Architecture and performance

  • A. Gunzinger
  • S. Mathis
  • W. Guggenbühl
Submitted Presentations
Part of the Lecture Notes in Computer Science book series (LNCS, volume 365)


In this paper a parallel computer architecture for real time image processing is described. The architecture centers on the direct mapping of a static dataflow graph into hardware: each node (or group of nodes) is replaced by a processing element.

A prototype of the system has been built. Many image processing algorithms run in real time at video rate.

Applications of the system are real time computer vision, real time image enhancement, robotics, and autonomous systems. A color classification algorithm for an autonomous vehicle guidance runs more than 100 times faster on this computer than on the WARP, a computer architecture especially built for image processing by the Carnegie Mellon University.


Systolic Array Image Processing Algorithm Data Flow Graph Match Unit Parallel Computer Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1989

Authors and Affiliations

  • A. Gunzinger
    • 1
  • S. Mathis
    • 1
  • W. Guggenbühl
    • 1
  1. 1.Electronics LaboratorySwiss Federal Institute of TechnologyZürichSwitzerland

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