Serial multiport memory multiprocessors

  • Litaize Daniel
  • Elkhlifi Fatimazahra
  • Hammami Omar
  • Lalam Mustapha
  • Mzoughi Abdelaziz
  • Sainrat Pascal
  • Salinier Jean-claude
Submitted Presentations
Part of the Lecture Notes in Computer Science book series (LNCS, volume 365)


This paper presents an inventive information exchange process between the main memory and cache equipped processors. It makes use of serial multiport memories and high throughput serial transmission supports. It is then possible to consider the realization of a multiprocessor with a common memory shared by several hundreds processors set with a performance level close to that of a crossbar network one's without having its disadvantages. This exchange process generates a family of possible architectures in which serial transfers of informations are parallelized, in the contrary of conventional architectures which serialize parallel transfers of informations.


Main Memory Shift Register Memory Module Processor Cycle Block Transfer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1989

Authors and Affiliations

  • Litaize Daniel
    • 1
  • Elkhlifi Fatimazahra
    • 1
  • Hammami Omar
    • 1
  • Lalam Mustapha
    • 1
  • Mzoughi Abdelaziz
    • 1
  • Sainrat Pascal
    • 1
  • Salinier Jean-claude
    • 1
  1. 1.Institut de Recherche en Informatique de Toulouse Laboratoire L.S.I.Université Paul SabatierToulouse Cedex

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