Advertisement

Serial multiport memory multiprocessors

  • Litaize Daniel
  • Elkhlifi Fatimazahra
  • Hammami Omar
  • Lalam Mustapha
  • Mzoughi Abdelaziz
  • Sainrat Pascal
  • Salinier Jean-claude
Submitted Presentations
Part of the Lecture Notes in Computer Science book series (LNCS, volume 365)

Abstract

This paper presents an inventive information exchange process between the main memory and cache equipped processors. It makes use of serial multiport memories and high throughput serial transmission supports. It is then possible to consider the realization of a multiprocessor with a common memory shared by several hundreds processors set with a performance level close to that of a crossbar network one's without having its disadvantages. This exchange process generates a family of possible architectures in which serial transfers of informations are parallelized, in the contrary of conventional architectures which serialize parallel transfers of informations.

Keywords

Main Memory Shift Register Memory Module Processor Cycle Block Transfer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

8. Bibliography

  1. [ArBa84]
    J. Archibald, J. Baer, "An economical solution to the cache coherence problem", The 11th Annual International Symposium on Computer Architecture", pp 355–362, June 1984.Google Scholar
  2. [AgSi88]
    A. Agarwal, R. Simoni, J. Hennessy, and M. Horowitz, "An evaluation of directory schemes for cache coherence", The 15th Annual International Symposium on Computer Architecture", pp 280–289, May 30-June 2 1988.Google Scholar
  3. [Bhan75]
    D. Bhandarkar, "Analysis of memory interference", IEEE trans. on computers, vol.C-2 sep. 1975.Google Scholar
  4. [Bhuy85]
    N. Bhuyan "Analysis of multiprocessor-memory interconnection networks", IEEE Trans. on computers, vol. C-34(3), March 1985.Google Scholar
  5. [BiDe86]
    P. Bitar, A. Despain "Multiprocessor Cache Synchronisation: issues, innovations, evolution", The 13th Annual International Symposium on Computer Architecture", pp 424–433.Google Scholar
  6. [CHVE88]
    H. Cheong and A. V. Veidenbaum, "A cache coherence scheme with fast selective invalidation", The 15th Annual International Symposium on Computer Architecture, pp 299–307, May 30-June 2, 1988.Google Scholar
  7. [DUBR82]
    M. Dubois, F. Briggs, "Effects of cache coherency in multiprocessors", IEEE Trans. on computers, C-31(11), November 1982.Google Scholar
  8. [CeFe78]
    L. Censier, P. Feautrier, "A new solution to coherence problems in multicache systems", IEEE Trans. on Computers, C-27(12), pp 1112–1118, December 1978.Google Scholar
  9. [GeAb88]
    Ed. F. Gehringer, J. Abullarade,and M. H. Gulyn, "A survey of commercial parallel processors", Comp. Arch. News, Vol 16–4 Sept 1988.Google Scholar
  10. [GoAg84]
    A. Goyal, T.Agerwala, "Performance analysis of future shared storage systems", IBM J. Res.Develop, January 1984.Google Scholar
  11. [GiLo88]
    GaAs IC data book & designer's guide. May 88. Gigabit Logic.Google Scholar
  12. [HoVe87]
    M. Holliday, M. Vernon, "Exact performance estimates for multiprocessor memory and bus interference", IEEE Trans. on computers, vol.C-34(3) March 1987.Google Scholar
  13. [Klei76]
    Kleinrock L., "Queueing systems", vol 2: computer applications. Wiley, New-York, 1976.Google Scholar
  14. [LeYL87]
    R. Lee, P. Yew, D. Lawrie, "Multiprocessor cache design considérations", The 14th Annual International Symposium on Computer Architecture", pp 253–262. 1987.Google Scholar
  15. [PaPa84]
    M. Papamarcos, J. Patel, "A low-overhead coherence solution for multiprocessors with private cache memories", The 11th Annual International Symposium on Computer Architecture", pp 348–354, June 1984.Google Scholar
  16. [Pate82]
    J. Patel "Analysis of multiprocessors with private cache memory", IEEE Trans. on computers, vol.C-31(4), April 1982.Google Scholar
  17. [ReFu87]
    D. Reed, R. Fujimoto "Multicomputer networks" The MIT Press 1987.Google Scholar
  18. [RuSe84]
    L. Rudolph Z. Segall, "Dynamic Decentralized cache schemes for MIMD parallel processors", The 11th Annual International Symposium on Computer Architecture", pp 340–347, 1984.Google Scholar
  19. [ScDu87]
    C. Scheurich, M. Dubois, "Correct memory operation ofcache-based multiprocessors", The 14th Annual International Symposium on Computer Architecture", pp 234–243, 1987.Google Scholar
  20. [Sten88]
    P. Stenström, "Reducing contention in shared-memory multiprocessors", Computer Nov. 88, pp 26–37.Google Scholar
  21. [Tang76]
    C. Tang, "Cache system design in the tightly coupled multiprocessor system", AFIPS proc. National Computer Conference, Vol. 45, pp 749–753, 1976.Google Scholar
  22. [Tows83]
    D. Towsley",An approximate analysis of multiprocessor systems", Proc.1983 ACM Sigmetrics conf. Meas and Mod.compt.syst, August 1983.Google Scholar
  23. [Triq88]
    Triquint Data sheets. 1988.Google Scholar
  24. [YePD83]
    P. Yeh, J. Patel, E. Davidson, "Shared cache for multiple-stream computer systems", IEEE Trans. on Computers, C-32(1), pp 38–47, January 1985.Google Scholar
  25. [YeYF85]
    W. Yen, D. Yen, K. Fu, "Data coherence problem in a multicache system", IEEE Trans. on Computers, C-34(1), pp 56–65, January 1985.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1989

Authors and Affiliations

  • Litaize Daniel
    • 1
  • Elkhlifi Fatimazahra
    • 1
  • Hammami Omar
    • 1
  • Lalam Mustapha
    • 1
  • Mzoughi Abdelaziz
    • 1
  • Sainrat Pascal
    • 1
  • Salinier Jean-claude
    • 1
  1. 1.Institut de Recherche en Informatique de Toulouse Laboratoire L.S.I.Université Paul SabatierToulouse Cedex

Personalised recommendations