Is there a minimum linewidth in integrated circuits?

Abstract

Reduction of linewidth is one of the most important problems in integrated circuit technology. The progress made is reviewed and the question whether there exists a minimum linewidth set by physical effects is discussed. It is suggested that two fundamental criteria exist which set such a limit. First, a minimum spot size, 2–3 rim, of the fabricating beam is determined by the Heisenberg uncertainity principle, by the minimum particle size in the resist, and by particle scattering. Second, statistics of pattern delinaation with the accompanying probability of an occasional deviation larger than a set tolerance limit sets a linewidth limit in the range 30–70 nm depending on the complexity of the circuit pattern. Other factors which enter in particular cases are also mentioned.