Abstract
To enhance system performance computer architectures tend to incorporate an increasing number of parallel execution units. This paper shows that the new generation of MD4-based customized hash functions (RIPEMD-128, RIPEMD-160, SHA-1) contains much more software parallelism than any of these computer architectures is currently able to provide. It is conjectured that the parallelism found in SHA-1 is a design principle. The critical path of SHA-1 is twice as short as that of its closest contender RIPEMD-160, but realizing it would require a 7-way multiple-issue architecture. It will also be shown that, due to the organization of RIPEMD-160 in two independent lines, it will probably be easier for future architectures to exploit its software parallelism.
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M. Bass, P. Knebel, D.W. Quint, W.L. Walker, “The PA 7100LC microprocessor: a case study of IC design decisions in a competitive environment,” HP Journal, Vol. 46, No. 2, April 1995, pp. 12–22.
D.P. Bhandarkar, Alpha implementations and architecture, Digital Press, Boston, MA, 1996.
G.E. Blelloch, “Programming parallel algorithms,” Communications of the ACM, Vol. 39, No. 3, 1996, pp. 85–97.
A. Bosselaers, R. Govaerts, J. Vandewalle, “Fast hashing on the Pentium,” Advances in Cryptology, Proceedings Crypto’96, LNCS 1109, N. Koblitz, Ed., Springer-Verlag, 1996, pp. 298–312.
C. Clapp, “Optimizing a fast stream cipher for VLIW, SIMD, and superscalar processors,” Fast Software Encryption, LNCS, E. Biham, Ed., Springer-Verlag, 1997, to appear.
Alpha architecture handbook, Version 3, Digital Equipment Corp., Maynard, MA, 1996.
H. Dobbertin, “Cryptanalysis of MD4,” Fast Software Encryption, LNCS 1039, D. Gollmann, Ed., Springer-Verlag, 1996, pp. 53–69.
H. Dobbertin, “The status of MD5 after a recent attack,” CryptoBytes, Vol. 2, No. 2, 1996, pp. 1–6.
H. Dobbertin, A. Bosselaers, B. Preneel, “RIPEMD-160: A Strengthened Version of RIPEMD,” Fast Software Encryption, LNCS 1039. D. Gollmann, Ed., Springer-Verlag, 1996, pp. 71–82. Final version available via ftp at http://ftp.esat.kuleuven.ac.be/pub/COSIC/bosselae/ripemd/.
FIPS 180-1, “Secure hash standard,” US Department of Commerce/NIST, Washington D.C., April 1995.
M. Flynn, “Very high-speed computing systems,” Proceedings of the IEEE, Vol. 54, No. 12, 1966, pp. 1901–1909.
S. Halevi and H. Krawczyk, “MMH: Software message authentication in the Gbit/second rates,” Fast Software Encryption, LNCS, E. Biham, Ed., Springer-Verlag, 1997, to appear.
J.L. Hennessy and D.A. Patterson, Computer architecture: a quantitative approach, 2nd edition, Morgan Kaufmann Publishers, San Francisco, 1996.
R. Lee, “Accelerating multimedia with enhanced microprocessors,” IEEE Micro, Vol. 15, No. 2, April 1995, pp. 22–32.
R. Lee, “Subword parallelism with MAX-2,” IEEE Micro, Vol. 16, No. 4, August 1996, pp. 51–59
D. Naccache, D. M’Raïhi, S. Vaudenay, D. Raphaeli, “Can DSA be improved? Complexity trade-offs with the Digital Signature Standard,” Advances in Cryptology, Proceedings Eurocrypt’94, LNCS 950, A. De Santis, Ed., Springer-Verlag, 1995, pp. 77–85.
K.S. McCurley, “A fast portable implementation of the secure hash algorithm, III,” Technical Report SAND93-2591, Sandia National Laboratories, 1994.
A. Peleg and U. Weiser, “MMX technology extension to the Intel architecture,” IEEE Micro, Vol. 16, No. 4, August 1996, pp. 42–50.
RIPE, “Integrity Primitives for Secure Information Systems. Final Report of RACE Integrity Primitives Evaluation (RIPE-RACE 1040),” LNCS 1007, A. Bosselaers and B. Preneel, Eds., Springer-Verlag, 1995.
R.L. Rivest, “The MD4 message-digest algorithm,” Request for Comments (RFC) 1320, Internet Activities Board, Internet Privacy Task Force, April 1992.
R.L. Rivest, “The MD5 message-digest algorithm,” Request for Comments (RFC) 1321, Internet Activities Board, Internet Privacy Task Force, April 1992.
M. Robshaw, “On recent results for MD2, MD4 and MD5,” Bulletin No. 4, RSA Laboratories, November 1996.
G.A. Slavenburg, S. Rathnam, H. Dijkstra, “The Trimedia TM-1 PCI VLIW media processor,” Hot Chips VIII Conference, Stanford University, Palo Alto, CA, 1996.
S.P. Song, M. Denman, J. Chang, “The PowerPc 604 RISC microprocessor,” IEEE Micro, Vol. 14, No. 5, October 1994, pp. 8–17.
P.H. Stakem, A practitioner’s guide to RISC microprocessor architecture, John Wiley & Sons, New York, 1996.
J. Touch, “Performance analysis of MD5,” Proceedings of ACM SIGCOMM’95, Comp. Comm. Review, Vol. 25, No. 4, 1995, pp. 77–86.
M. Tremblay, J.M. O’Connor, V. Narayanan, L. He, “VIS speeds new media processing,” IEEE Micro, Vol. 16, No. 4, August 1996, pp. 10–20.
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Bosselaers, A., Govaerts, R., Vandewalle, J. (1997). SHA: A Design for Parallel Architectures?. In: Fumy, W. (eds) Advances in Cryptology — EUROCRYPT ’97. EUROCRYPT 1997. Lecture Notes in Computer Science, vol 1233. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-69053-0_24
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DOI: https://doi.org/10.1007/3-540-69053-0_24
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