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International Workshop on Field Programmable Logic and Applications

FPL 1997: Field-Programmable Logic and Applications pp 294–303Cite as

Data scheduling to increase performance of parallel accelerators

  • Custom Computing and Codesign
  • Conference paper
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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1304))

Abstract

The paper presents a general data and task scheduling technique for parallel accelerators with one or more processing modules and the capability for local and shared memory access. Multiple tasks and their data are mapped onto the processing modules and the host, providing a high degree of parallelism. The system performance is enhanced by avoiding unnecessary data transfers. It is shown, how overall system performance can be increased by appropriate data distribution.

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References

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Author information

Authors and Affiliations

  1. University of Kaiserslautern, Erwin-Schrödinger-Straße, D-67663, Kaiserslautern, Germany

    R. W. Hartenstein, J. Becker, M. Herz & U. Nageldinger

Authors
  1. R. W. Hartenstein
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  2. J. Becker
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  3. M. Herz
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  4. U. Nageldinger
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Editor information

Wayne Luk Peter Y. K. Cheung Manfred Glesner

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© 1997 Springer-Verlag Berlin Heidelberg

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Hartenstein, R.W., Becker, J., Herz, M., Nageldinger, U. (1997). Data scheduling to increase performance of parallel accelerators. In: Luk, W., Cheung, P.Y.K., Glesner, M. (eds) Field-Programmable Logic and Applications. FPL 1997. Lecture Notes in Computer Science, vol 1304. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63465-7_234

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  • DOI: https://doi.org/10.1007/3-540-63465-7_234

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-63465-2

  • Online ISBN: 978-3-540-69557-8

  • eBook Packages: Springer Book Archive

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