Skip to main content

Automatic identification of swappable logic units in XC6200 circuitry

  • Reconfiguration II
  • Conference paper
  • First Online:
Field-Programmable Logic and Applications (FPL 1997)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1304))

Included in the following conference series:

Abstract

A Swappable Logic Unit (SLU) is an FPGA-based logic circuit that can be managed by a virtual hardware operating system. Since the SLU concept is still in its infancy, it is unreasonable to expect circuit design systems to be enhanced to include SLU awareness at this stage. Therefore, this paper describes a tool that can be used as a back end to any XC6200 circuit design system. It analyses XC6200 circuitry, to detect SLUs and then collect information about their external interfaces. This information is needed by an operating system so that it can manage the SLUs when they are in use.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Brebner, “A Virtual Hardware Operating System for the Xilinx XC6200”, Proc. 6th International Workshop on Field-Programmable Logic and Applications, Springer LNCS 1142, 1996, pp.327–336.

    Google Scholar 

  2. Brebner, “CHASTE: a Hardware-Software Co-design Testbed for the Xilinx XC6200”, Proc. 4th Reconfigurable Architecture Workshop, ITpress Verlag, 1997, pp.16–23.

    Google Scholar 

  3. Brebner, “The Swappable Logic Unit: a Paradigm for Virtual Hardware“, Proc. 5th Annual IEEE Symposium on Custom Computing Machines, IEEE Computer Society Press 1997.

    Google Scholar 

  4. Burns, Donlin, Hogg, Singh and Watt, “A Dynamic Reconfiguration Run Time System“, Proc. 5th Annual IEEE Symposium on Custom Computing Machines, IEEE Computer Society Press 1997.

    Google Scholar 

  5. Kean, Churcher and Wilkie: “XC6200 Fastmap Processor Interface,” Proc. 5th International Workshop on Field Programmable Logic and Applications, Springer LNCS 975, 1995, pp.36–43.

    Google Scholar 

  6. Luk, Shirazi and Cheung, “Compilation Tools for Run-Time Reconfigurable Designs“, Proc. 5th Annual IEEE Symposium on Custom Computing Machines, IEEE Computer Society Press 1997.

    Google Scholar 

  7. Xilinx Inc., XC6200 advance product specification, Xilinx 1996.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Wayne Luk Peter Y. K. Cheung Manfred Glesner

Rights and permissions

Reprints and permissions

Copyright information

© 1997 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Brebner, G. (1997). Automatic identification of swappable logic units in XC6200 circuitry. In: Luk, W., Cheung, P.Y.K., Glesner, M. (eds) Field-Programmable Logic and Applications. FPL 1997. Lecture Notes in Computer Science, vol 1304. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63465-7_222

Download citation

  • DOI: https://doi.org/10.1007/3-540-63465-7_222

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-63465-2

  • Online ISBN: 978-3-540-69557-8

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics