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A new hardware structure for implementation of soft morphological filters

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Computer Analysis of Images and Patterns (CAIP 1997)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1296))

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Abstract

A new hardware structure for implementation of soft morphological filters is presented in this paper. This is based on the modification of the majority gate technique. A pipelined systolic array architecture suitable to perform real-time soft morphological filtering is presented as an illustrative example. The processing times of the proposed hardware structure do not depend on the data window size and its hardware complexity grows linearly with the number of its inputs.

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References

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Authors and Affiliations

  1. Laboratory of Electronics Section of Electronics and Information Systems Technology Department of Electrical and Computer Engineering, 67100, Xanthi, Greece

    A. Gasteratos, I. Andreadis & P. Tsalides

Authors
  1. A. Gasteratos
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  2. I. Andreadis
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  3. P. Tsalides
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Editor information

Gerald Sommer Kostas Daniilidis Josef Pauli

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© 1997 Springer-Verlag Berlin Heidelberg

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Gasteratos, A., Andreadis, I., Tsalides, P. (1997). A new hardware structure for implementation of soft morphological filters. In: Sommer, G., Daniilidis, K., Pauli, J. (eds) Computer Analysis of Images and Patterns. CAIP 1997. Lecture Notes in Computer Science, vol 1296. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63460-6_154

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  • DOI: https://doi.org/10.1007/3-540-63460-6_154

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-63460-7

  • Online ISBN: 978-3-540-69556-1

  • eBook Packages: Springer Book Archive

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