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Systematic design of 3-dimensional fixed-size array processors

  • Theory
  • Conference paper
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Parallel Computing Technologies (PaCT 1997)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1277))

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Abstract

A formalized method for a space-time mapping of algorithms onto three-dimensional fixed-size array processors without long interconnections is proposed. Initial algorithms are represented by dependence graphs which are constructed on the basis of recurrence equations. Some special forms of partitioning and spatial mapping of the graph models are considered to provide within the framework of locally parallel globally sequential strategy of partitioning both fixed size of the arrays and the locality of interconnections between processor elements. Conflict-free scheduling of the model is developed. Minimizing of the time requirements is considered. The parameters of scheduling providing the minimization are found.

This research was supported by the Fund of Fundamental Investigations of the Republic of Belarus, grant F-181.

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Authors and Affiliations

  1. Institute of Mathematics, Academy of Sciences of Belarus, Surganova str., 11, 220072, Minsk, Belarus

    N. A. Likhoded & A. A. Tiountchik

Authors
  1. N. A. Likhoded
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  2. A. A. Tiountchik
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Victor Malyshkin

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© 1997 Springer-Verlag Berlin Heidelberg

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Likhoded, N.A., Tiountchik, A.A. (1997). Systematic design of 3-dimensional fixed-size array processors. In: Malyshkin, V. (eds) Parallel Computing Technologies. PaCT 1997. Lecture Notes in Computer Science, vol 1277. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63371-5_7

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  • DOI: https://doi.org/10.1007/3-540-63371-5_7

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-63371-6

  • Online ISBN: 978-3-540-69525-7

  • eBook Packages: Springer Book Archive

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