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Trace table based approach for pipelined microprocessor verification

  • Jun Sawada
  • Warren A. HuntJr.
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1254)

Abstract

This paper presents several techniques for formally verifying pipelined microprocessor implementations that contain out-of-order execution and dynamic resolution of data-dependent hazards. Our principal technique models the trace of executed instructions using a table-based representation called a MAETT. We express invariant properties of pipelined implementations by specifying relations between fields in the MAETT. To show the viability of this technique, we have proved the correctness of a simple out-of-order completion pipelined microprocessor design using the ACL2 theorem prover. This verification was performed incrementally by proving that the specified relations hold for all microarchitectural states reachable from a flushed implementation state, eventually permitting us to prove that the entire pipelined machine design implements its ISA specification.

Keywords

Register File Correctness Criterion Execution Unit Architectural State Verification Approach 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1997

Authors and Affiliations

  • Jun Sawada
    • 1
  • Warren A. HuntJr.
    • 2
  1. 1.Department of Computer SciencesUniversity of TexasAustinUSA
  2. 2.Computational Logic, Inc.AustinUSA

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