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STARI: A case study in compositional and hierarchical timing verification

  • Serdar Taşiran
  • Robert K. Brayton
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1254)

Abstract

In [TAKB96], we investigated techniques for checking if one real-time system correctly implements another and developed theory for hierarchical proofs and assume-guarantee style reasoning. In this study, using the techniques of [TAKB96], we verify the correctness of the timing of the communication chip STARI.

Keywords

Abstract Model Clock Signal Timing Verification Gate Level Refinement Check 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

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    M. R. Greenstreet STARI: A Technique for High-Bandwidth Communication. PhD thesis, Princeton University, 1993.Google Scholar
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    S. Taşiran, R. Alur, R. P. Kurshan, and R. K. Brayton Verifying Abstractions of Timed Systems. In Proc. of the 7th Intl. Conf. on Concurrency Theory, CONCUR '96, LNCS 1119, pages 546–562, Springer-Verlag, 1996.Google Scholar
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    http://www-cad.eecs.berkeley.edu/~serdar/stari.htmlGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1997

Authors and Affiliations

  • Serdar Taşiran
    • 1
  • Robert K. Brayton
    • 1
  1. 1.Department of Electrical Engineering and Computer SciencesUniversity of California at BerkeleyUSA

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