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Some progress in the symbolic verification of timed automata

  • Marius Bozga
  • Oded Maler
  • Amir Pnueli
  • Sergio Yovine
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1254)

Abstract

In this paper we discuss the practical difficulty of analyzing the behavior of timed automata and report some results obtained using an experimental BDD-based extension of KRONOS. We have treated examples originating from timing analysis of asynchronous boolean networks and CMOS circuits with delay uncertainties and the results outperform those obtained by previous implementations of timed automata verification tools.

Keywords

Reachable State Timing Verification Time Automaton Asynchronous Circuit Time Transition System 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1997

Authors and Affiliations

  • Marius Bozga
    • 1
  • Oded Maler
    • 1
  • Amir Pnueli
    • 2
  • Sergio Yovine
    • 1
  1. 1.Centre EquationVerimagGièresFrance
  2. 2.Dept. of Computer ScienceWeizmann Inst.RehovotIsrael

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