Synchronization support in I/O adapter based SCI clusters

Abstract

This paper examines synchronization support of two generations of SCI adapters from Dolphin Interconnect Solutions and compares the functionality to similar support on Digital's Memory Channel. Memory Channel enforces sequential consistency across the interconnect, while SCI allows store reordering. This gives SCI a potential performance payoff by allowing more flexible pipelining of data through the interconnect. The lower number of ordering constraints also reduces hardware complexity, but moves the complexity to software. For a straightforward implementation of message passing this overhead is significant. A new software algorithm, the valid flag algorithm, is introduced to improve this situation. A new hardware lock support mechanism is proposed to facilitate efficient locks in absence of lock support on the I/O bus. Performance of the simple message passing protocol is compared to the suggested valid flag protocol. The valid flag protocol reduces latency of a small message by 50% and also increases throughput for pipelined, small messages significantly.