FIR filtering with FPGAs using quadrature sigma-delta modulation encoding

Abstract

This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. The method uses a tunable quadrature sigma-delta modulator to re-quantise a real- or complex-valued input stream to a reduced precision, so removing the requirement for a full multiplier in the filter hardware. This makes the technique very attractive for implementation using FPGAs. The re-quantisation process preserves the dynamic range of the signal components contained in the bandwidth of the filter, while shifting the re-quantisation noise to the spectral region to be rejected by the filter. The filter architecture described and its implementation using Xilinx FPGAs is presented.