Abstract
Technology mapping for lookup-table based FPGAs is usually performed in two steps. In the first step, Boolean functions are decomposed into smaller functions. The second step finds a circuit of LUTs covering the decomposed network. In this paper, we describe our novel performance-directed functional decomposition approach. Having this powerful decomposition approach as well as a depth-optimal covering algorithm (FlowMap) at hand, we evaluate different performance-directed technology mapping flows for LUT-based FPGAs. Experimental results demonstrate a significant area and circuit depth reduction by using our functional decomposition approach in the decomposition step.
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
References
Xilinx Inc., San Jose, CA-95125, The Programmable Logic Data Book, 1994.
R. J. Francis, J. Rose, and Z. Vranesic, “Technology mapping of lookup table-based FPGAs for performance,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 568–571, 1991
K.-C. Chen, J. Cong, Y. Ding, A. B. Kahng, and P. Trajmar, “DAG-Map: Graph-based FPGA technology mapping for delay optimization,” IEEE Design & Test of Computers, pp. 7–20, Sept. 1992.
J. Cong and Y. Ding, “Flowmap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems CAD, vol. 13, pp. 1–12, Jan. 1994. in ACM/IEEE Design Automation Conference (DAC), pp. 213–218, 1993.
J. Cong and Y.-Y. Hwang, “Simultaneous depth and area minimization in LUT-based FPGA mapping,” in ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 68–74, Feb. 1995.
J. Cong and Y. Ding, “On nominal delay minimization in LUT-based FPGA technology mapping,” in ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 82–88, Feb. 1995.
H. Yang and D. F. Wong, “Edge-Map: Optimal performance driven technology mapping for iterative LUT based FPGA designs,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 150–155, 1994.
R. Murgai, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Performance directed synthesis for table look up programmable gate arrays,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 572–575, 1991.
P. Sawkar and D. Thomas, “Performance directed technology mapping for look-up table based FPGAs,” in ACM/IEEE Design Automation Conference (DAC), pp. 208–212, 1993.
J. Cong and Y. Ding, “Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 110–114, Nov. 1993.
J. Cong and Y.-Y. Hwang, “Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design,” in ACM/IEEE Design Automation Conference (DAC), pp. 726–729, June 1996.
E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Sequential circuit design using synthesis and optimization,” in IEEE International Conference on Computer Design (ICCD), pp. 328–333, Oct. 1992.
C. Legl, B. Wurth, and K. Eckl, “A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs,” in ACM/IEEE Design Automation Conference (DAC), pp. 730–733, June 1996.
H. A. Curtis, “A generalized tree circuit,” Journal of the ACM, vol. 8, pp. 484–496, 1961.
J. P. Roth and R. M. Karp, “Minimization over boolean graphs,” IBM Journal of Research and Development, pp. 227–238, 1962.
B. Wurth, K. Eckl, and K. Antreich, “Functional multiple-output decomposition: Theory and an implicit algorithm,” in ACM/IEEE Design Automation Conference (DAC), pp. 54–59, June 1995.
C. Legl, B. Wurth, and K. Eckl, “An implicit algorithm for support minimization during functional decomposition,” in European Design and Test Conference (ED&TC), pp. 412–417, March 1996.
H. J. Touati, H. Savoj, and R. K. Brayton, “Delay optimization of combinational logic circuits by clustering and partial collapsing,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 188–191, 1991.
R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, “MIS: A multiple-level logic optimization of combinational logic,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems CAD, vol. 6, pp. 1062–1081, Nov. 1987.
K. J. Singh, A. R. Wang, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Timing optimization of combinational logic,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 282–285, 1988.
A. H. Farrahi and M. Sarrafzadeh, “Complexity of the lookup-table minimization problem for FPGA technology mapping,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems CAD, vol. 13, pp. 1319–1332, Nov. 1994.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1996 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Legl, C., Eckl, K., Wurth, B. (1996). Performance-directed technology mapping for LUT-based FPGAs — What role do decomposition and covering play?. In: Hartenstein, R.W., Glesner, M. (eds) Field-Programmable Logic Smart Applications, New Paradigms and Compilers. FPL 1996. Lecture Notes in Computer Science, vol 1142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61730-2_2
Download citation
DOI: https://doi.org/10.1007/3-540-61730-2_2
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-61730-3
Online ISBN: 978-3-540-70670-0
eBook Packages: Springer Book Archive