Abstract
Rapid prototyping is a well accepted method in microelectronics. Early validation of an ASIC design is possible through emulation using FPGAs. Thus, specification errors can be eliminated and the overall development time and costs are reduced significantly. One of the main task in ASIC emulation is netlist partitioning. The approach we implemented is tailored to the architectural characteristics of application specific embedded controllers for mechatronic applications. It is based on a hierarchical partitioning strategy.
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© 1996 Springer-Verlag Berlin Heidelberg
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Ober, U., Glesner, M., Herpel, HJ. (1996). CAPpartx: Computer aided prototyping partitioning for Xilinx FPGAs, a hierarchical partitioning tool for rapid prototyping. In: Hartenstein, R.W., Glesner, M. (eds) Field-Programmable Logic Smart Applications, New Paradigms and Compilers. FPL 1996. Lecture Notes in Computer Science, vol 1142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61730-2_11
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DOI: https://doi.org/10.1007/3-540-61730-2_11
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