Minimizing congestion of layouts for ATM networks with faulty links

Abstract

We consider the problem of constructing virtual path layouts for an ATM network consisting of a complete network K _n of n processors in which a certain number of links may fail. Our main goal is to construct layouts which tolerate any configuration of up to f layouts and have a least possible congestion. First, we study the minimal congestion of 1-hop f-tolerant layouts in K _n . For any positive integer f we give upper and lower bounds on this minimal congestion and construct f-tolerant layouts with congestion corresponding to the upper bounds. Our results are based on a precise analysis of the diameter of the network K _n[$\mathcal{F}$] which results from K _n by deleting links from a set $\mathcal{F}$ of bounded size. Next we study the minimal congestion of h-hop f-tolerant layouts in K _n , for larger values of the number h of hops. We give upper and lower bounds on the order of magnitude of this congestion, based on results for 1-hop layouts. Finally, we consider a random, rather than worst case, fault distribution. Links fail independently with constant probability p}<1. Our goal now is to construct layouts with low congestion that tolerate the existing faults with high probability. For any p}<1, we show such layouts in K _n , with congestion O(log n).

On leave from Institute of Informatics, Warsaw University, ul. Banacha 2, 02-097, Warszawa, Poland.

Research supported in part by NSERC (Natural Sciences and Engineering Research Council of Canada) grants.

Research supported in part by NSERC grant OGP 0008136.