Advertisement

Design error diagnosis in sequential circuits

  • Ayman Wahba
  • Dominique Borrione
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 987)

Abstract

We present a new diagnostic algorithm for localising design errors in sequential circuits. The specification and the implementation may have different number of state variables, and different state encoding. The algorithm is based on the new concept of possible next states describing the possible states of the circuit due to the existence of the error. Results obtained on benchmark circuits show that the error is always found, with an execution time proportional to the product of the circuit size, and the length of the test sequences used.

Keywords

Search Space Finite State Machine State Line Test Vector Design Error 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    J. C. Madre, O. Coudert, J. P. Billon, “Automating the Diagnosis and the Rectification of Design Errors with PRIAM,” Proceedings of ICCAD'89, pp. 30–33, 1989.Google Scholar
  2. 2.
    K. A. Tamura, “Locating Functional Errors in Logic Circuits,” Proceedings of 26th Design Automation Conference (DAC'89), pp. 185–191, 1989.Google Scholar
  3. 3.
    S. Y. Kuo, “Locating Logic Design Errors via Test Generation and Don't Care Propagation,” Proceedings of EURO-DAC'92, pp. 466–471, 1992.Google Scholar
  4. 4.
    P. Y. Chung, Y. M. Wang, I. N. Hajj, “Diagnosis and Correction of Logic Design Errors in Digital Circuits,” Proceedings of 30th Design Automation Conference (DAC'93), 1993.Google Scholar
  5. 5.
    A. M. Wahba, E. J. Aas, “Verification and Diagnosis of Digital Systems by Ternary Reasoning,” Lecture Notes on Computer Science No. 683, Springer Verlag, pp. 55–67, May 1993.Google Scholar
  6. 6.
    Q. H. Zhang, C. Trullemans, “Logic Verification of Incomplete Functions and Design Error Location,” Lecture Notes on Computer Science No. 683, Springer Verlag, pp. 68–79, May 1993.Google Scholar
  7. 7.
    M. Tomita, T. Yamamoto, F. Sumikawa, and K. Hirano, “Rectification of Multiple Logic Design Errors in Multiple Output Circuits,” Proceedings of the 31st Design Automation Conference(DAC'94), 1994.Google Scholar
  8. 8.
    A. Wahba, and D. Borrione, “Design Error Diagnosis in Logic Circuits using Diagnosis-Oriented Test Patterns,” Research Report RR-940-I, ARTEMIS-IMAG, Grenoble, France, June 1994.Google Scholar
  9. 9.
    Q. Zhang, “Logic Verification and Design Error Diagnosis for Combinational Circuits,” Ph.D. Thesis, Université Catholique de Louvain, Belgium, Feb. 1995.Google Scholar
  10. 10.
    M. Fujita, “Methods for Automatic Design Error Correction in Sequential Circuits,” Proceedings of European Conference on Design Automation with The European Event in ASIC Design, 1993, pp. 76–80, 1993.Google Scholar
  11. 11.
    M. S. Abadir, J. Ferbuson, and T. E. Kirkland, “Logic Design Verification via Test Generation,” IEEE Transactions on Computer-Aided Design, Vol. 7, No. 1, pp. 138–148, January 1988.Google Scholar
  12. 12.
    Z. Kohavi, Switching and Finite Automata Theory, McGraw-Hill Book Edition, 1978.Google Scholar
  13. 13.
    E. J. Aas, K. A. Klingshheim, and T. Steen, “Quantifying Design Quality: A Model and Design Experiments,” Proc. EURO-ASIC'92, IEEE Computer Society, pp. 172–177, 1992.Google Scholar
  14. 14.
    M. A. Breuer and A. D. Friedman, Diagnosis and Reliable Design of Digital Systems, New York: Computer Science Press, 1976.Google Scholar
  15. 15.
    F. Brglez, D. Bryan, and K. Kozminski, “Combinational Profiles of Sequential Benchmark Circuits,” Proceedings of International Symposium of Circuits and Systems (ISCAS'89), Portland, OR, May 1989.Google Scholar
  16. 16.
    A. Lioy, P. L. Montessoro, and S. Gai, “A Complexity Analysis of Sequential ATPG,” Proceedings of IEEE International Symposium of Circuits and Systems (ISCAS'89), pp. 1946–1949, May 1989.Google Scholar
  17. 17.
    G. Cabodi, P. Camurati, S. Quer, “Symbolic Exploration of Large Circuits with Enhanced Forward/Backward Traversal,” Proceedings of EURO-DAC'94, pp. 22–27, Grenoble, France, Sept. 1994.Google Scholar
  18. 18.
    D. Borrione, H. Eveking, “Formal Verification of Hardware Designs,” To appear in Journal of the Brazilian Computer Society, Special Issue on Electronic Design Automation, Nov. 1995.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1995

Authors and Affiliations

  • Ayman Wahba
    • 1
  • Dominique Borrione
    • 1
  1. 1.ARTEMIS LaboratoryJoseph Fourier UniversityGrenoble Cedex 9France

Personalised recommendations