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FPLD-implementation of computations over finite fields GF(2m) with applications to error control coding

  • Arithmetic and Signal Processing
  • Conference paper
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Field-Programmable Logic and Applications (FPL 1995)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 975))

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Abstract

This paper investigates the implementation of computations over finite fields GF(2m) using field-programmable logic devices (FPLDs). Implementation details for addition/subtraction, multiplication, square, inversion, and division are given with mapping results for Xilinx LCAs, Altera CPLDs and Actel ACT FPGAs. As an application example, mapping results for complete encoders for error-correcting codes are also presented. Finally, new opportunities emerging from FPLD technology for data transmission systems with dynamic code adaption are discussed.

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Authors and Affiliations

  1. Dept. of Computer Science, University of Hamburg, Vogt-Koelln-Str. 30, 22527, Hamburg, Germany

    André Klindworth

Authors
  1. André Klindworth
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Editor information

Will Moore Wayne Luk

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© 1995 Springer-Verlag Berlin Heidelberg

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Klindworth, A. (1995). FPLD-implementation of computations over finite fields GF(2m) with applications to error control coding. In: Moore, W., Luk, W. (eds) Field-Programmable Logic and Applications. FPL 1995. Lecture Notes in Computer Science, vol 975. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60294-1_120

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  • DOI: https://doi.org/10.1007/3-540-60294-1_120

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-60294-1

  • Online ISBN: 978-3-540-44786-3

  • eBook Packages: Springer Book Archive

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