Abstract
Self-timing provides an attractive alternative to synchronous design in order to overcome scalability problems and fixed processing time. The self-timed approach abolishes the need for a clock signal at any level in the system, and instead uses local control mechanisms to ensure the circuit behaves correctly independent of communication delays. This paper introduces self-timed design strategies developed for use in massively parallel array architectures. These strategies promote bit-serial elastic control and data communication in scalable array architectures. A number of different solutions will be proposed and are assessed on a cost/performance basis resulting on application driven guidelines for design of communication strategies.
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© 1994 Springer-Verlag Berlin Heidelberg
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Hogg, R.S., Lloyd, D.W., Hughes, W.I. (1994). Self-timed communication strategies for massively parallel systolic architectures. In: Buchberger, B., Volkert, J. (eds) Parallel Processing: CONPAR 94 — VAPP VI. VAPP CONPAR 1994 1994. Lecture Notes in Computer Science, vol 854. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58430-7_49
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DOI: https://doi.org/10.1007/3-540-58430-7_49
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