Abstract
In single bus, shared memory multiprocessors with private caches, the cache coherence problem affects the system design at various levels. This paper analyzes which hardware and workload components have the most significant influence on the cache coherence overhead and, therefore, need to be considered when designing the multiprocessor architecture. Subsequently, we incorporate these parameters (i.e., the cache coherence protocol, the cache coherence block size and the sharing of data inherent in the parallel workload) into a model by using a finite state machine. This model also allows a fast and thorough evaluation of the sharing behavior of parallel applications.
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References
Agarwal, A.; Gupta, A.: “Memory-Reference Characteristics of Multiprocessor Applications under MACH”, Proc. 1988 ACM SIGMETRICS Conf. Measurement Modeling Comp. Syst., Vol. 16, No. 1, pp. 215–225, May 1988.
Archibald, J.; Baer, J.: “An Evaluation of Cache Coherence Solutions in Shared Bus Multiprocessors”, ACM Trans. Comput. Syst., Vol. 4, No. 4, pp. 273–298, Nov. 1986.
Chiang, M.; Sohi, G.S.: “Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment”, IEEE Trans. Comput, Vol. 41, No. 3, pp. 297–317, March 1992.
Dubois, M.; Briggs, J.C.: “Shared Data Contention in a Cache Coherence Protocol”, Proc. 1988 Int. Conf. Parallel Processing, Vol. 1, pp. 146–155, Aug. 1988.
Eggers, S.J.: “Simplicity Versus Accuracy in a Model of Cache Coherency Overhead”, IEEE Transactions on Computers, Vol. 40, No. 8, pp. 893–906, Aug. 1991.
Goodman, J.R.: “Using Cache Memory to Reduce Processor-Memory Traffic”, Proc. 10th Annu. Symp. Comput. Arch., pp. 124–131, June 1983.
Kattner, R.: “Optimierung von parallelen Programmen durch Task-Clustering”, Techn. Rep., IRB, Uni. of Hannover, Oct. 1993.
Lee, D.D.; Kong, S.I. u.a.: “A VLSI Chip Set for a Multiprocessor Workstation”, IEEE Journal of Solid-State Circuits, Vol. 24, No. 6, pp. 1688–1697, Dec. 1989.
Covington, R.C.; Madala, S.; Metha, V.; Jump, J.R.; Sinclair, J.B.: “The Rice Parallel Processing Testbed”, Proc. 1988 ACM SIGMETRICS, Performance Evaluation Review, Vol. 16, No. 1, pp. 4–11, 1988.
Stenström, P.: “A Survey of Cache Coherence Schemes for Multiprocessors”, Computer, Vol. 23, No. 6, pp. 12–24, June 1990.
Veenstra, J.E.; Fowler, R.J.: “A Performance Evaluation of Optimal Hybrid Cache Coherency Protocols”, Techn. Rep. 414, Uni. Rochester, Comp. Science Dep., Rochester, N.Y., May 1992.
Vernon, M.K.; Holliday, M. A.: “Performance Analysis of Multiprocessor Cache Consistency Protocols Using Generalized Timed Petri Nets”, Techn. Rep. 618, Comp. Science Dep., UW-Madison, Nov. 1985.
Wood, D.A.; Hill, M.D. et al.: “A Model for Estimating Trace-Sample Miss Ratios”, Performance Evaluation Review, Vol. 19, pp. 79–89, May 1991.
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© 1994 Springer-Verlag Berlin Heidelberg
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Kattner, R., Eger, M., Müller-Schloer, C. (1994). Modeling cache coherence overhead with geometric objects. In: Buchberger, B., Volkert, J. (eds) Parallel Processing: CONPAR 94 — VAPP VI. VAPP CONPAR 1994 1994. Lecture Notes in Computer Science, vol 854. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58430-7_39
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DOI: https://doi.org/10.1007/3-540-58430-7_39
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