Abstract
In vector multiprocessor systems, collisions in the interconnection network and conflicts in the memory modules are the main causes of the performance degradation. In this work we propose to synchronize the access to the memory system so that streams can be accessed with the minimum achievable latency if their elements are requested out of order. The mechanism uses a blockinterleaved storage scheme and works for strides belonging to the most common families of strides found in real programs. The hardware required is also described and its complexity is shown to be equivalent to the complexity of the address generator when the processors request the elements in order.
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References
J.W.C. Fu and J.H. Patel, “Data Prefetching in Multiprocessor Vector Cache Memories”, Int. Symp. on Computer Architecture, pp. 54–63, 1991.
Q. Yang, “Introducing a New Cache Design into Vector Computers”, IEEE Trans. on Computers, vol. 42, no. 12, pp. 1411–1424, 1993.
P.M. Kogge, “The Architecture of Pipelined Computers”, McGraw-Hill, New York, 1981.
P. Budnik and D. J. Kuck, “The Organization and Use of Parallel Memories”, IEEE Trans. on Computers, vol. 20, no. 12, pp. 1566–1569, 1971.
J. Frailong, W. Jalby and J. Lenfant, “XOR-schemes: A Flexible Data Organization in Parallel Memories”, Int. Conf. on Parallel Processing, pp. 276–283, 1985.
B.R. Rau, M.S. Schlansker and D.W.L. Yen, “The Cydra 5 Stride-Insensitive Memory System”, Int. Conf. on Parallel Processing, pp. 242–246, 1989.
G.F. Pfister et al., “The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture”, Int. Conf. on Parallel Processing, pp. 764–771, 1985.
D.T. Harper III, “Address Transformations to Increase Memory Performance”, Int. Conf. on Parallel Processing, pp. 237–241, 1989.
A. Seznec and J. Lenfant, “Interleaved Parallel Schemes: Improving Memory Throughput on Supercomputers”, Int. Symp. on Computer Architecture, pp. 246–255, 1992.
M. Peiron, M. Valero et al., “Synchronized Access to Streams in Multiprocessors”, IEEE Technical Committee on Computer Architecture Newsletter, pp. 37–41, Fall 1993.
H. Shing and L.M. Ni, “A Conflict-free Memory Design for Multiprocessors”, Supercomputing91, pp. 46–55, 1991.
M. Valero, T. Lang et al., “Increasing the Number of Strides for Conflict-Free Vector Access”, Int. Symp. on Computer Architecture, pp. 372–381, 1992.
M. Peiron, M. Valero and E. Ayguadé, “Synchronized Access to Streams in SIMD Vector Multiprocessors”, Int. Conference on Supercomputing, 1994.
M. Valero, M. Peiron and E. Ayguadé, “Optimal Access to Streams in Multimodule Memories”, DAC/UPC Research Report 94/01
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© 1994 Springer-Verlag Berlin Heidelberg
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Valero, M., Peiron, M., Ayguadé, E. (1994). Memory access synchronization in vector multiprocessors. In: Buchberger, B., Volkert, J. (eds) Parallel Processing: CONPAR 94 — VAPP VI. VAPP CONPAR 1994 1994. Lecture Notes in Computer Science, vol 854. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58430-7_37
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DOI: https://doi.org/10.1007/3-540-58430-7_37
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