Abstract
For many real-time and scientific applications, it is desirable to perform signal and image processing algorithms by means of special hardware in very high speed. With the advent of VLSI technology. large collections of processing elements can be used to achieve high-speed computations. In such designs, some level of fault tolerance must be obtained to ensure the validity of the results. Fermat number transforms (FNT's) are attractive for the implementation of digital convolution because the computations are carried out in modular arithmetic which offer three advantages: no round-off error, no multiplications in the transform, and decomposition into fast algorithm analogous to the FFT. In this paper we present a fault-detectable array architecture for the fast implementation of Fermat number transform. The results show that the design offers concurrent error detection (CED) using very low hardware and time overheads.
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References
Abraham J. Banerjee P, Chen C, Fuchs W and Reddy A, “Fault Tolerance Techniques for Systolic Arrays”, IEEE Comput., Vol. 20, pp. 65–74, July 1987.
Agarwal R C and Burrus C S, “Fast Convolution Using Fermat Number Transforms With Applications to Digital Filtering”, IEEE Trans. ASSP, Vol. 22, No. 2, pp. 87–97, April 1974.
Agarwal R C and Burrus C S, “Fast One-Dimensional Digital Convolution by Multidimensional Techniques”, IEEE Trans. ASSP, Vol. 22, No. 1, pp. 1–10, February 1974.
Haddad R and Parsons T, “Digital Signal Processing Theory, Applications, and Hardware”, Freeman and Company, 1991.
Jou J and Abraham J, “Fault-Tolerant FFT Networks”, IEEE Trans. Computers, Vol. 37, No. 5, pp. 548–561, May 1988.
Lala P, “Fault Tolerant & Fault Testable Hardware Design”, Prentice-Hall, 1984.
Leibowitz L M, “A Simplified Binary Arithmetic for the Fermat Number Transform”, IEEE Trans. ASSP, Vol. 24, No. 5, pp. 356–359, October 1976.
Mead C, “Introduction to VLSI systems”, Addison-Wesley, 1980.
McClellan J, “Hardware Realization of Fermat Number Transform”, IEEE Trans. ASSP, Vol. 24, No. 3, pp. 216–225, June 1976.
Tinder R F. “Digital Engineering Design”, Prentice-Hall 1991.
Truong T K, Reed I S, Yeh C S, Shoa H M, “Parallel VLSI Architecture for a Digital Filter of Arbitrary Length Using Fermat Number Transforms”, Proceedings of IEEE international conference on circuits and computers (ICCC 82), New York, USA, Sept. 28–Oct, 1, 1982.
Wakerly J, “Error Detecting Codes, Self-checking Circuits and Applications”, Elsevier North-Holland. INC., 1978.
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© 1994 Springer-Verlag Berlin Heidelberg
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Tahir, J.M., Dlay, S.S., Gorgui-Naguib, R.N., Hinton, O.R. (1994). Concurrent error detection in fast FNT networks. In: Echtle, K., Hammer, D., Powell, D. (eds) Dependable Computing — EDCC-1. EDCC 1994. Lecture Notes in Computer Science, vol 852. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58426-9_151
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DOI: https://doi.org/10.1007/3-540-58426-9_151
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