Abstract
This paper presents a new technique for improving the performance of a synchronous circuit configured as a look-up table based FPGA without changing the initial circuit configuration except for latch location. One of the most significant benefits realized by this approach is that the time-consuming and user-uncontrollable reconfiguration processes, i.e., re-mapping, re-placement and re-routing, are unnecessary to improve circuit performance.
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© 1994 Springer-Verlag Berlin Heidelberg
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Miyazaki, T., Nakada, H., Tsutsui, A., Yamada, K., Ohta, N. (1994). A speed-up technique for synchronous circuits realized as LUT-based FPGAs. In: Hartenstein, R.W., Servít, M.Z. (eds) Field-Programmable Logic Architectures, Synthesis and Applications. FPL 1994. Lecture Notes in Computer Science, vol 849. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58419-6_72
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DOI: https://doi.org/10.1007/3-540-58419-6_72
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