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Fault modeling and test generation for FPGAs

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Field-Programmable Logic Architectures, Synthesis and Applications (FPL 1994)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 849))

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Abstract

This paper derives a fault model for one-time programmable FPGAs from the general functional fault model and an algorithm to perform test generation according to this model. The new model is characterized by the abstraction of functional faults from a set of possible implementations of a circuit. In contrast to other functional-level test generation procedures a fault coverage of 100% can be achieved regardless of the final implementation of the circuit.

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References

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Authors and Affiliations

  1. Institute of Electronic Design Automation, Department of Electrical Engineering, Technical University of Munich, 80290, Munich, Germany

    Michael Hermann & Wolfgang Hoffmann

Authors
  1. Michael Hermann
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  2. Wolfgang Hoffmann
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Editor information

Reiner W. Hartenstein Michal Z. Servít

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© 1994 Springer-Verlag Berlin Heidelberg

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Hermann, M., Hoffmann, W. (1994). Fault modeling and test generation for FPGAs. In: Hartenstein, R.W., Servít, M.Z. (eds) Field-Programmable Logic Architectures, Synthesis and Applications. FPL 1994. Lecture Notes in Computer Science, vol 849. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58419-6_64

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  • DOI: https://doi.org/10.1007/3-540-58419-6_64

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-58419-3

  • Online ISBN: 978-3-540-48783-8

  • eBook Packages: Springer Book Archive

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